
module flow_led(
    input               sys_clk,
    input               sys_rst_n,
    
    output  reg[3:0]    led
);

//延时计数
reg [23:0]  delay_cnt;

always  @(posedge sys_clk or negedge sys_rst_n)   begin
    if(!sys_rst_n)
        delay_cnt <= 1'b0;
    else
        if(delay_cnt < 24'd1000_0000)
            delay_cnt <= delay_cnt + 1'b1;
        else   
            delay_cnt <= 24'd0;       
end

always  @(posedge sys_clk or negedge sys_rst_n)   begin
    if(!sys_rst_n)
        led <= 4'b0001;
    else
        if(delay_cnt == 24'd1000_0000)
            led[3:0] <= {led[2:0],led[3]};   //{}括号表示位拼接的方式，2:0向左移1位，3放到第一位
        else   
            led <= led;       
end


endmodule